1. The Field of the Invention
The present invention relates to the field of modem serial port communications, between a host computer modem and various mobile communication devices. More specifically the invention relates to a parallel to serial asynchronous hardware assisted DSP interface, as used in modem communication across digital or AMPS cellular networks, high speed digital telephone lines, and other wireless communication networks.
2. The Relevant Technology
The extensive development of powerful portable personal computers, low cost high speed modems, and digital cellular telephones, creates the infrastructure required for a convenient and efficient mobile data communication network. Unfortunately, one of the main obstacles to creating this type of mobile data communication network is the difficulty of integrating each of these components.
Mobile network designers continue to be burdened by communication standards established years ago for what was then three configurations. For example, modems of the kind used with portable personal computers are generally not intended to physically and electrically interface with digital cellular telephone networks, instead hardware interfaces and connectors focus on land based analog telephone networks. While some solutions to the compatibility and integration problems exist, each configuration contains defects that make the specific implementation either commercially prohibitive or impractical.
One configuration is to integrate the digital modem and digital cellular telephone into one unit, thereby creating a wireless modem with an integrated digital cellular transceiver. This configuration is undesirable for several reasons. First, the hardware necessary for digital cellular communication is expensive. Second, a user will generally need both a digital cellular modem and a digital cellular telephone. This configuration requires the user to carry expensive duplicate digital communication hardware around, not to mention the duplicate monthly digital phone service fee.
A second configuration uses a customized data interface on a digital cellular telephone that slows down the reception and transmittal of data to and from the personal computer. One problem with this configuration is that it does not take advantage of the high speed data transfer rates that are possible with a digital cellular phone. Instead, communication rates are limited to the traditional slower transfer rates associated with analog cellular phone lines. An additional problem with this configuration is that the customized data interface requires either special software, hardware, or both to operate effectively. This type of interface will often require a special digitally compatible modem to communicate with the digital cellular interface. This non-standard software and hardware requirement hampers the ability of the computer to run many common communication software programs that utilize a proprietary protocol or require standard serial connections but provide their own drivers. A useful example is the software necessary to connect with many Internet online services.
Another unacceptable configuration is to provide a hardware interface in a separate physical package from the modem. This interface simulates a standard RJ 11 telephone jack to the conventional modem and connects on the other side to the data input/output of a digital cellular telephone. The main disadvantage of this configuration is the need for additional hardware to be carried with the computer and added whenever a digital communications link is to be established. A secondary disadvantage is the drain placed on the battery of the laptop computer, the hardware interface, or the cellular telephone by the generation of high voltage signals required for the input to the modem, like the ring signal. Finally, the modem signal may be degraded through the hardware interface connections resulting in a potential loss of data before the information even gets onto the digital cellular network.
The invention of faster communication technology actually amplify these old throughput problem areas. The Universal Asynchronous Receiver Transmitter (UART) has long been accused of slowing down the serial communication data pipeline. Traditionally, cellular communication rates were limited by the serial nature of the analog cellular phone or the Advanced Mobile Phone Service (AMPS) cellular phone. Fortunately, the UART interface was barely sufficient to satisfy the transfer rate requirements of the modem. But increasing the speed of transmission and reception network only amplify the UART problems. With the advent of digital cellular telephones, transmission speeds exceed the capabilities of the standard UART. In fact the UART is being stressed on both sides as the V.90 protocol further enhances the modem""s expected communication rate with the host computer.
Presently, there are two main improvements which are applying stress to the modem-to-digital phone network interface. First, the data communication rates of digital modems have increased substantially over previous levels. Second, the possible transmission rate across a digital cellular network is substantially higher than across the analog cellular network. Because the interface remains the same, it becomes the bottleneck between the DSP and the network. The result is that the digital modem DSP is able to quickly transfer data to the interface, but must either process each byte serially at substantial overhead or wait for the interface to complete serialization before the data can be transmitted across the cellular line. Often the overhead to the DSP can cause the user to notice system performance degradation while the DSP is stalling to send or receive the next byte.
Cellular modems must communicate with the cellular phone via a proprietary protocol established by the cellular manufacturer. In the case of the AMPS cellular standard, the communication is traditionally a low rate serial communication for control, and analog for data to be transmitted. These low rates are achieved by the DSP via a General Purpose Input Output (GPIO) port, but at a significant DSP overhead cost. Newer digital phones have higher rate communication interfaces that combine control and data, such that the DSP overhead at these rates would use too many DSP resources. What is needed in high speed digital cellular digital communication is an interface which allows the UART to function at a very high throughput level, while at the same time minimizing the drain upon the digital signal processor and personal computer. These particular features should be implemented utilizing hardware as software would increase the overhead pressure on the DSP.
Traditionally, the modem would send an interrupt signal to the DSP. The DSP would then pass on an interrupt to the personal computer telling the computer that data was waiting for it to pick up. Due to the slow transfer rate, the computer could easily handle the interrupt and return to performing its previous program function without any noticeable delay to the user. With the new high speed transfers of smaller data blocks, the DSP is continually waiting for the computer to send more data, creating more interrupts and therefore interfering with the overall performance of the personal computer. Often these asynchronous data transfers become too cumbersome, requiring the DSP to virtually stop work on other projects until the data is processed. In essence the DSP is churning over the data blocks. This processor overhead drain is amplified when the device is connected to a cellular phone as the delays in verifying the quality of the data may cause the user of the personal computer, to notice a slowing in performing standard functions.
The dramatic increase in transmission capability has created a unique problem for modems trying to communicate across digital cellular networks. What is needed is an interface that can increase the throughput to an AMPS cellular or digital phone without increasing the overhead to the DSP. An improved hardware interface would enhance the ability of the modem to transfer larger data blocks based on the particular protocol being employed without requiring replacement of interface hardware components.
What is needed is a simple hardware solution integrated into the modem which allows for connectivity between the digital cellular telephone and the portable personal computer at a low cost and yet still reliable system. This hardware should support the widely available communication software conformed to the accepted IEEE standards, and alternatively permit data communication across a conventional telephone network.
It is an object of the present invention to provide a hardware driven AMPS cellular or digital phone interface that can be driven with very little overhead to the DSP.
Another object of the present invention is to improve the synchronous parallel to asynchronous serial throughput rate and overall DSP Input/Output efficiency through the implementation of specialized buffering registers that allow the interface to optimize the buffer threshold and fill levels based upon the protocol specifications provided to the interface by the DSP.
A further object of the present invention is to provide added ability to the DSP to communicate with the computer via a standard serial port as a debugging tool or as a method to achieve accurate performance analysis.
The invention describes a parallel to serial asynchronous hardware assisted DSP interface or serial data module. One advantage of the invention is that the interface can be driven with very little overhead to the DSP. Furthermore, the hardware settings in the interface can be adjusted by the DSP for optimal performance using various asynchronous protocols. Optimization occurs through a calculation made by the DSP to determine the most efficient FIFO size for a particular protocol. A useable space FIFO is developed from the real FIFO by establishing a threshold point using the registers to indicate the best fill level for the interface. This flexibility makes the invention valuable as a serial asynchronous debugging tool. The various configurations are also useful in obtaining an accurate performance analysis of a computer""s serial data transfer efficiency.
The serial data module contains three main sub-modules designed to assist the DSP with serial data operations. The first module is a register module or asynchronous serial data (ASD) module. The second module is a hardware timer, utilized to assist with complicated timing issues as well as coordinating stale counts and data sampling. Finally, an EEPROM control module provides a hardware implementation of the DSP code used to program the EEPROM so that the DSP does not have to run the protocol and dramatically reducing the DSP overhead associated with changing protocols. The EEPROM controller can be erased and rewritten by either the DSP or the ASD. Another element is the bus controller with an independent ASD Tx control module and an ASD Rx control module. The data bus controller connects with a parallel DSP interface that allows the DSP to write data in a parallel fashion and have the hardware shift the data out in a serial fashion. The DSP interface including the IRQ signals, the external clock signal, the address bus, the read and write data buses, the reset control signal, the module selection and address buses, and the strobe and write signals. The ASD module will receive serial data in and transform the data so that the DSP can read parallel data. By performing the data serialization the DSP is relieved of the intensive tasks associated with the serializing of the data and creating the desired serial interface. The hardware timer can be used to assist with any timing critical operations, but is inserted primarily to help the DSP time very slow serial data communications whenever the ASD module does not perform the appropriate protocol.
The DSP communicates with the ASD module through registers found in the serial data module. Data is written to the Tx FIFO through the DSP to ASD FIFO register (DAF). Data is read from the Rx FIFO from ASD to DSP FIFO register (ADF). The ASD is reset and enabled utilizing a third register called the control register. The control register acts like a control register for the serial data module, by allowing the DSP to make changes through a write to the register. The status of interrupts and other functions can be read by the DSP through a separate fourth register, called the status register or Serial Data Status Register (SDSR). FIFO thresholds for interrupts are contained in two registers called the ASD Rx FIFO Threshold Register (ARFTR) and the ASD TX FIFO Threshold Register (ATFTR). The Rx stale count is also written to yet another register called the Rx Stale Count Register (RSCR).
The serial data module is able to communicate with the outside world through two asynchronous serial data interface pins. The two pins that provide the serial data interface are the Asynchronous Serial Data Out (ASDO) pin and the Asynchronous Serial Data In (ASDI). This interface is totally asynchronous and data transfer is enabled when the appropriate bits in the Control Register are set and the data is sent through the serialization process. The serial data module also generates the start bit for Tx data and waits for the start bit on the ASDI pin.
To receive data the ASDI pin is polled at the system clock rate. This oversampling of the ASDI pin at the system clock rate increases the accuracy of the system. After each system clock cycle a bit sample is evaluated as being high or low. A counter averages the bit samples received by adding one if the bit sample was high and subtracting one if the bit sample was low. At the end of the bit period designated by the BRGR, the bit is assigned a one if the counter is positive, or a zero if it is zero or negative. Oversampling the incoming bits increases the accuracy of incoming data when compared to data collected using a single bit sample method. While a single bit sample could produce accurate data, the process subjects the data to a greater risk of degradation. When a start bit is detected on the ASDI pin and the transfer enable bit is enabled in the control register, the receive data state machine is initialized and the ASDI pin is oversampled at the system clock rate until a byte is received. When the byte is received it is subsequently loaded into the Rx FIFO as shown in FIGS. 2 and 3.
To send data the transfer begins with a generation of a start bit immediately upon the availability of the data in the Tx FIFO and the corresponding setting of the transmit enable bit in the control register. The byte is then shifted out serially with the least significant bit (LSB) first. When the last bit (the MSB) is shifted out a stop bit is then generated signifying the end of a byte frame. The timing diagram and state machine controlling this process is demonstrated in FIGS. 4 and 5.
The serial data module removes substantial overhead from the DSP by receiving parallel data reads and converting that data into asynchronous data frames to be sent out over the serial communication lines. The serial data module further optimizes communication between the DSP and the module by establishing flexible threshold values which allow the module to be optimized for a particular protocol and to take advantage of the high speed digital cellular networks. This flexibility is allows for the adaptation of the serial data module to various wireless communication protocols including AMPS cellular and digital cellular.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.